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NXP Semiconductors /MIMXRT1021 /DCDC /REG3

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Interpret as REG3

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TRG0 (sel0)TARGET_LP 0 (fullfreq)MINPWR_DC_HALFCLK 0 (enable)DISABLE_STEP

TARGET_LP=sel0, MINPWR_DC_HALFCLK=fullfreq, DISABLE_STEP=enable

Description

DCDC Register 3

Fields

TRG

Target value of VDD_SOC
TARGET_LP

Low Power Target Value

0 (sel0): 0.9 V

1 (sel1): 0.925 V

2 (sel2): 0.95 V

3 (sel3): 0.975 V

4 (sel4): 1.0 V
MINPWR_DC_HALFCLK

Set DCDC clock to half frequency for continuous mode

0 (fullfreq): DCDC clock remains at full frequency for continuous mode

1 (halffreq): DCDC clock set to half frequency for continuous mode
DISABLE_STEP

Disable Step

0 (enable): Enable stepping for the output of VDD_SOC of DCDC

1 (disable): Disable stepping for the output of VDD_SOC of DCDC

Links

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Register License

Copyright 2016-2020 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data